1. Field of the Invention
The present invention relates to an image information transmitting system and, more particularly, to an image information transmitting system capable of performing high-efficiency coding.
2. Related Background Art
For example, a high-efficiency coding scheme for a television signal is known as an image information transmitting scheme of this type. In this high-efficiency coding scheme for the television signal, since a transmission band must be narrowed, a so-called MIN-MAX method for reducing the average number of bits per pixel is employed. The MIN-MAX method will be described below.
A television signal has strong correlation with time in a space. When an image is divided into small blocks, the blocks often have only a small dynamic range due to local correlation. A local dynamic range is obtained in each block, and adaptive coding is performed to perform highly efficient data compression.
This coding scheme will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic block diagram of an image information transmitting system as a prior art. The image information transmitting system includes an input terminal 301. An analog signal obtained by raster-scanning, e.g., a television signal is sampled at a predetermined frequency, and data (n bits/sample) is input to the input terminal 301. The digital image data having 2.sup.n gradation levels are supplied to a pixel block dividing circuit 302.
FIG. 2 is a view showing a state wherein one-frame pixel data are divided into pixel blocks. In the pixel block dividing circuit 302, the one-frame pixel data are temporarily stored in a memory or the like. As shown in FIG. 2, the pixel data are read out in units of blocks each having (l.times.m) pixels, i.e., l pixels in the horizontal direction (to be referred to as an H direction hereinafter) and m pixels in the vertical direction (to be referred to as a V direction thereinafter). That is, the data are output in units of pixel blocks.
FIG. 3 shows a format of each pixel block. This pixel block contains pixel data D.sub.1,1 to D.sub.m,l. Image data output from the pixel block dividing circuit 302 are input to a MAX value detection circuit 303, a MIN value detection circuit 304, and a timing adjusting circuit 305. Of all the pixel data (D.sub.1,1 to D.sub.m,l) in each pixel block, a pixel (D.sub.max) having a MAX value and a pixel (D.sub.min) having a MIN value are detected by and output from the detection circuits 303 and 304, respectively.
The timing adjusting circuit 305 delays all the pixel data by a period required to cause the MAX and MIN value detection circuits 303 and 304 to detect the pixels D.sub.max and D.sub.min. The pixel data are sent to a divided value converting circuit 306 in units of pixel blocks in a predetermined order. For example, data are sent in an order of D.sub.1,1, D.sub.2,1, D.sub.3,1, . . . , D.sub.m,1, D.sub.1,2, . . . D.sub.m,2, . . . , D.sub.1,(l-1), . . . D.sub.m,(l-1), D.sub.1,l, . . . , and D.sub.m,l in units of pixel blocks
All the pixel data (D.sub.1,1 to D.sub.m,l) and MAX and MIN values (D.sub.max and D.sub.min) of each pixel block are input to the divided value converting circuit 306 and are compared with 2.sup.k (where k is an integer smaller than n) quantization levels between the values D.sub.max and D.sub.min, thereby obtaining k-bit division codes (.DELTA..sub.1,1, to D.sub.m,l). The quantization state is shown in FIG. 4A.
As shown in FIG. 4A, the division code .DELTA..sub.i,j is output as a k-bit binary code. The obtained k-bit division code .DELTA..sub.i,j and the n-bit values D.sub.max and D.sub.min are converted into serial data by parallel-to-serial (P-S) converters 307, 307', and 307", respectively. One of the outputs from the P-S converters is selected by a data selector 308, thus obtaining serial data shown in FIG. 5A. The data output from the data selector 308 is added with a p-bit error correction code (FIG. 5B) by an error correction code adding circuit 309. The output from the error correction code adding circuit 309 is processed by a first-in first-out (FIFO) memory 310 along the time axis so as to obtain a predetermined data transmission rate. In addition, an output from the FIFO memory 310 is added with a synchronizing signal by a synchronizing signal adding circuit 311. The obtained signal is sent out from an output terminal 312 onto a transmission line (a magnetic recording/reproducing system such as a VTR).
The synchronizing signal is added in units of pixel blocks or every plurality of pixel blocks. The operation timings of the above circuits are determined on the basis of timing signals output from a timing control circuit 313.
FIG. 6 is a block diagram showing a schematic arrangement of a receiving side corresponding to a data transmitting side shown in FIG. 1. The receiving side in FIG. 6 includes an input terminal 821 for receiving transmission data highly efficiently coded at the transmitting side. The input transmission signal is supplied to a synchronizing signal separating circuit 822 and an error correction circuit 823.
The synchronizing signal separating circuit 822 separates a synchronizing signal from the input transmission data and sends the separated synchronizing signal to the error correction circuit 823 and a timing control circuit 831.
The error correction circuit 823 separates the error correction code from the transmission data in synchronism with the synchronizing signal supplied from the synchronizing signal separating circuit 822, detects a data error generated along the transmission line in accordance with the error correction code, corrects this error, and supplies the corrected data to a data selector 824.
The timing control circuit 831 controls operating timings of the respective circuits on the receiving side on the basis of the synchronizing signal supplied from the synchronizing signal separating circuit 822.
The data selector 824 separates the transmission data into the n-bit data D.sub.max and D.sub.min and the k-bit codes .DELTA..sub.i,j quantized between the values D.sub.max and D.sub.min. These separated data are supplied to serial-to-parallel (S-P) converters 825 and 825', respectively, and are converted into parallel data thereby. The MAX and MIN value data D.sub.max and D.sub.min converted into the parallel data by the S-P converter 825 are latched by latch circuits 826 and 827, respectively. The latched MAX and MIN value data D.sub.max and D.sub.min are supplied to a divided value inverting circuit 828. The division code .DELTA..sub.i,j associated with all the pixel data in each pixel block are output from the S-P converter 825' in a predetermined order and are supplied to the divided value inverting converter 828.
FIG. 4B is a view showing a state wherein representation data D.sub.i,j ' associated with the original pixel data are decoded from the division code .DELTA..sub.i,j and the MAX and MIN value data D.sub.max and D.sub.min. As shown in FIG. 4B, the representation value is set to be an intermediate value between the adjacent ones of 2.sup.k quantization levels between the values D.sub.max and D.sub.min. The resultant n-bit representation value data (D.sub.1,1 ' to D.sub.m,l ') from the divided value inverting circuit 828 are output in units of pixel blocks in the predetermined order. In a scan convert circuit 829, output data from the divided value inverting circuit 828 is converted in an order corresponding to raster scan, and the obtained data appears as decoded image data at an output terminal 830.
In the conventional arrangement, however, in order to correct a data error occurring on the transmission line, the error correction code must be added to the transmission data at the transmitting side, and the obtained data is sent onto the transmission line. At the receiving side, the data error occurring on the transmission line is corrected by using the error correction code. Redundancy of the transmission data is increased by the error correction code, and transmission efficiency cannot be improved much.